Graphics processing unit
The "Xenos" graphics processing unit (GPU) is a custom chip designed by ATI. (Developed under the name "C1", sometimes "R500")[25] The chip contains two separate silicon dies: the parent GPU and the daughter eDRAM.
* 315 million transistors total
* 500 MHz parent GPU (90 nm TSMC process, 235 million transistors)
* 300 MHz 10 MB daughter embedded DRAM framebuffer (90 nm process, 50 million transistors)
o NEC designed eDRAM die includes additional logic for color, alpha blending, Z/stencil buffering, and anti-aliasing.
o 8 render output units
* 48-way parallel floating-point dynamically-scheduled shader pipelines
o Unified shader architecture (each pipeline is capable of running either pixel or vertex shaders)
o
Support for DirectX 9.0 Shader Model 3.0 and DirectX 10 Shader Model 4.0
o MEMEXPORT shader function
o 2 shader ALU operations per pipeline per cycle (1 vec4 and 1 scalar, co-issued)
o 96 programmable shader operations per cycle[26]
o 48 billion shader operations per second ( 96 ops per clock cycle x 500mhz )
o 240 GFLOPS programmable[26]
* 16 filtered or unfiltered texture samples per clock
* Maximum polygon performance: 500 million triangles per second
* Texel fillrate: 8 gigatexel per second fillrate (16 textures x 500 MHz)
* Pixel fillrate: 16 gigasamples per second fillrate using 4X multisample anti aliasing (MSAA), or 32 gigasamples using Z-only operation; 4 gigapixels per second without MSAA (8 ROPs x 500 MHz)[25]
* Dot product operations: 24 billion per second or 33.6 billion per second theoretical maximum when summed with CPU operations